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PD - 94818
IRF520NPBF
Advanced Process Technology Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Fully Avalanche Rated Lead-Free Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry.
HEXFET(R) Power MOSFET
D
VDSS = 100V RDS(on) = 0.20
G S
ID = 9.7A
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 srew
Max.
9.7 6.8 38 48 0.32 20 91 5.7 4.8 5.0 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
--- 0.50 ---
Max.
3.1 --- 62
Units
C/W
11/5/03
IRF520NPBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. 100 --- --- 2.0 2.7 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. --- 0.11 --- --- --- --- --- --- --- --- --- --- 4.5 23 32 23
Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.20 VGS = 10V, ID = 5.7A 4.0 V VDS = VGS, ID = 250A --- S VDS = 50V, ID = 5.7A 25 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 25 ID = 5.7A 4.8 nC VDS = 80V 11 VGS = 10V, See Fig. 6 and 13 --- VDD = 50V --- ID = 5.7A ns --- RG = 22 --- RD = 8.6, See Fig. 10 Between lead, 4.5 --- 6mm (0.25in.) nH G from package 7.5 --- and center of die contact 330 --- VGS = 0V 92 --- pF VDS = 25V 54 --- = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge
Min. Typ. Max. Units --- --- --- --- --- --- --- --- 99 390 9.7 A 38 1.3 150 580 V ns nC
Conditions MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25C, IS = 5.7A, VGS = 0V TJ = 25C, IF = 5.7A di/dt = 100A/s
D
S
Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) VDD = 25V, starting T J = 25C, L = 4.7mH RG = 25, IAS = 5.7A. (See Figure 12) ISD 5.7A, di/dt 240A/s, VDD V(BR)DSS, TJ 175C Pulse width 300s; duty cycle 2%.
IRF520NPBF
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
I , Drain-to-Source Current (A) D
I , Drain-to-Source Current (A) D
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10
10
4.5V 20s PULSE WIDTH TC = 175C
1 10 100
4.5V
1 0.1
20s PULSE WIDTH TC = 25C
1 10
A
100
1 0.1
A
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = 9.5A
I D , Drain-to-Source Current (A)
2.5
2.0
TJ = 25C
10
TJ = 175C
1.5
1.0
0.5
1 4 5 6 7
V DS= 50V 20s PULSE WIDTH
8 9 10
A
0.0 -60 -40 -20 0 20 40 60
VGS = 10V
80 100 120 140 160 180
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRF520NPBF
600
500
Ciss
400
300
Coss
V GS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
20
I D = 5.7A
16
VDS = 80V VDS = 50V VDS = 20V
C, Capacitance (pF)
12
8
200
Crss
100
4
0 1 10 100
A
0 0 5 10
FOR TEST CIRCUIT SEE FIGURE 13
15 20 25
A
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
10s
I D , Drain Current (A)
10 100s
TJ = 175C
10
TJ = 25C
1ms 1 10ms
1 0.4 0.6 0.8 1.0
VGS = 0V
1.2
A
1.4
0.1 1
TC = 25C TJ = 175C Single Pulse
10 100
1000
A
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRF520NPBF
VDS
10.0
RD
VGS RG
D.U.T.
+
8.0
- VDD
ID , Drain Current (A)
10V
6.0
Pulse Width 1 s Duty Factor 0.1 %
4.0
Fig 10a. Switching Time Test Circuit
VDS 90%
2.0
0.0
25
50
TC , Case Temperature ( C)
75
100
125
150
175
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRF520NPBF
EAS , Single Pulse Avalanche Energy (mJ)
VDS L
200
D.U.T. RG + V - DD
TOP
160
BOTTOM
ID 2.3A 4.0A 5.7A
10 V
IAS tp
0.01
120
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp VDD VDS
80
40
0
VDD = 25V
25 50 75 100 125 150
175
A
Starting TJ , Junction Temperature (C)
IAS
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
IRF520NPBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
+ +
-
RG
* * * *
dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
IRF520NPBF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048)
4 15.24 (.600) 14.84 (.584)
1.15 (.045) MIN 1 2 3
LEAD ASSIGNMENTS IGBTs, CoPACK 1 - GATE 21- GATE DRAIN 1- GATE 32- DRAINSOURCE 2- COLLECTOR 3- SOURCE 3- EMITTER 4 - DRAIN
LEAD ASSIGNMENTS
HEXFET
14.09 (.555) 13.47 (.530)
4- DRAIN
4.06 (.160) 3.55 (.140)
4- COLLECTOR
3X 3X 1.40 (.055) 1.15 (.045)
0.93 (.037) 0.69 (.027) M BAM
3X
0.55 (.022) 0.46 (.018)
0.36 (.014)
2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
2.92 (.115) 2.64 (.104)
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 ASSEMBLED O N WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIO NAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER
Note: "P" in assembly line position indicates "Lead-Free"
DATE CODE YEAR 7 = 1997 WEEK 19 LINE C
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.11/03
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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